This invention relates to integrated circuits and, more particularly, to functional testing and debugging of integrated circuit designs.
The Ser. No. 10/956,854 patent application discloses a beneficial design approach for System on a Chip (SoC) devices, where each core is encompassed with a wrapper that includes a functionally reconfigurable module (FRM). The advance in the art disclosed in the Ser. No. 10/956,854 patent application incorporates configurable circuits within the FRM that perform assertion checking.
In assertion checking, a collection of conditions is identified that are expected to hold true during the operation of a properly working SoC, and the SoC is exercised to determine that, in fact, this is true. To perform assertion checking, the tested SoC receives various stimuli (test inputs, or normal operation type inputs), and the resulting SoC states are checked against the collection of assertions. Typically assertion checking is done in simulation, because it is not practical to implement many assertion in fixed hardware. The invention described in the Ser. No. 10/956,854 patent application removed this restriction by allowing assertions to be efficiently implemented in reconfigurable hardware. In hardware, assertion checking can be of two types: “at-speed” assertion checking, or “single-step” assertion checking. In “at-speed” assertion checking, only the directly observable signals of a core are available for the assertion checking, so assertions that require knowledge of the states of flip-flops that are internal to the SoC cannot be checked. Moreover, the assertions need to be checked with circuitry that works at the clock's speed. That is, the checking of all of the assertions must be completed within one operational clock period. In “single-step” assertion checking, the internal flip-flops of the SoC are interconnected to form a scan chain (the circuitry for forming the scan chain having been included in the SoC design in accord with conventional design practices), the data of the formed scan chain is scanned out, and the information thus obtained is analyzed to determine whether any of the assertions fire. The scanned-out data is re-inserted into the SoC in order to return the SoC to the state in which it was prior to scanning out the scan chain data.
The Ser. No. 10/956,854 patent application also discloses the “Continuous Single Step” (CSS) mode, which makes possible automatic checking of assertions after every functional clock. That is, the SoC under test is activated in its normal mode (mode A) for a single period of the operational clock, and then moved to its assertion checking mode (mode B). During the assertion checking mode the scan chain is formed, the required bits are extracted from scan chains (and re-injected, to return the circuit to its operational state), and tested against the set of assertions. If none of the assertions fires, the SoC is again activated in its normal operation for one period of the operational clock, and again moves to its assertion-checking mode.
Clearly, at-speed assertion checking is faster than CSS assertion checking, but also clearly, at-speed assertion checking cannot check assertions that require knowledge of values of internal flip-flops that are not directly observable. Also, it may happen that some assertions may be too large to be implemented in the reconfigurable hardware available on chip (i.e., require more hardware than can be configured in the FRM).